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data sheet cmos digital integrated circuits p p p p pd2845gr 1 v, 1.3 ma, 94mhz pll synthesizer lsi for pager system 1994 document no. p12150ej2v0ds00 (2nd edition) (previous no. ic-3291) date published february 1997 n pi di j data sheet description p pd2845gr is a pll synthesizer lsi for pager system. this lsi is manufactured using low voltage cmos process and therefore realized the low power consumption pll operated on 1 v, 1.3 ma. this lsi is packaged in 16 pin plastic ssop suitable for high-density surface mounting. so, this product contributes to produce a long-life- battery and physically-small pager system. features ? operating frequency : input frequency : f in = 10 mhz to 94 mhz reference oscillating frequency : f xtal = 12.8 mhz ? low supply voltage : pll block : v dd1 = 1.00 v to 1.15 v @ f in = 10 mhz to 70 mhz v dd1 = 1.05 v to 1.15 v @ f in = 10 mhz to 94 mhz charge pump block: v dd2 = 3.0 v 300 mv ? low power consumption i dd = 1.3 ma typ. @ f in = 70 mhz, f xtal = 12.8 mhz ? equipped with power-save function serial data can be received in power-save mode. ? packaged in 16 pin plastic ssop suitable for high-density surface mounting. ordering information part number package supplying form p pd2845gr-e1 16 pin plastic ssop (225 mil) embossed tape 12 mm wide. qty 2.5 k/reel pin 1 is in tape pull-out direction. p pd2845gr-e2 16 pin plastic ssop (225 mil) embossed tape 12 mm wide. qty 2.5 k/reel pin 1 is in tape roll-in direction. * to order evaluation samples, please contact your local nec sales office (order number : p pd2845gr). pin assignment v dd1 f in gnd fr reset eo eop eon xi xo le clk data ps nc v dd2 (top view) caution electro-static sensitive devices
2 p p p p pd2845gr internal block diagram 16 15 14 13 12 11 10 9 xi xo le le fv fr gate gate clk clk data data ps nc v dd2 v dd1 f in gnd fr reset eo eop eon 1 2 3 4 5 6 7 8 in amp 1/2 prescaler 32/33 prescaler test circuit phase comparator phase detector error out pch open drain nch open drain reference divider 13 bit latch 13 bit latch 18 bit divider 13 bit timer shift register 23 bit 5 bit
3 p p p p pd2845gr pin explanation pin no. pin name i/o explanation for function 1v dd1 supply voltage to pll block 2f in i frequency input 3 gnd ground 4 fr o test pin for monitor. normally used as pll, output l should be selected by test bit and this pin should be opened. (refer to setting for reference counter on 11 page) 5 reset i test pin for monitor reset. (refer to reset on 12 page) normally used as pll, this pin should be grounded. 6 eo o internal charge pump output. in the case of passive filter, this output should be used. input signal phase f p vs. reference signal f r f p > f r : low output f p < f r : high output f p = f r : high-impedance 7 8 eop eon o o outputs for external charge pump. in the case of active filter, this outputs should be used. eop : pch open drain eon : nch open drain 9v dd2 supply voltage to charge pump. 10 nc non connection. 11 ps i control bias input for power-save (refer to power-save on 12 page). 12 data i data input for divided ratio. 13 clk i clock input for shift register. 14 le i latch enable input. 15 16 xo xi o i xtal oscillator connection pin. eop eon
4 p p p p pd2845gr absolute maximum ratings (unless otherwise specified, t a = +25 c ) supply voltage v dd1 e 0.3 to 2.0 v v dd2 e 0.3 to 6.0 v input voltage v i1 e 0.3 to v dd1 +0.3 (except for data, clk, le, ps pin) v v i2 e 0.3 to 6.0 (data, clk, le, ps) v output voltage v o1 e 0.3 to v dd1 +0.3 (xo, fr) v v o2 e 0.3 to v dd2 +0.3 (eo, eop, eon) v output current i o 10 ma operating ambient temperature t a e 10 to +50 c storage temperature t stg e 55 to +125 c recommended operating range parameter symbol min. typ. max. unit v dd1 1.0 1.05 1.1 v v dd2 2.85 3.0 3.15 v operating ambient temperature t a e 10 +25 +50 c supply voltage
5 p p p p pd2845gr electrical characteristics dc performance (unless otherwise specified, v dd1 = 1.00 v to 1.15 v, v dd2 = 2.70 to 3.30 v, t a = e e e e 10 to +50 c) parameter symbol min. typ. max. unit conditions supply voltage v dd1 1.00 1.05 1.15 v pll operation v dd2 2.70 3.0 3.30 v p/d charge pump block circuit current i dd1 1.3 2.2 ma f in = 70 mhz, 0.2 v p-p . fxtal = 12.8 mhz xtal osc in. v dd1 = 1.0 v to 1.1 v v dd2 = 2.85 v to 3.15 v data retain current i dr 1.0 10 p a no input signal, v dd1 = 1.1 v high level output current1 *1 i oh1 e 1.0 ma eo, eop pin. v dd2 = 2.85 v v oh = v dd2 e 0.5 v high level output current2 *1 i oh2 e 0.5 ma xo pin. v oh = v dd1 e 0.5 v high level output current3 *1 i oh3 e 0.1 ma fr pin. v oh = v dd1 e 0.5 v low level output current1 *2 i ol1 1.0 ma eo, eon pin. v dd2 = 2.85 v v ol = 0.5 v low level output current2 *2 i ol2 0.4 ma xo pin. v ol = 0.5 v low level output current3 *2 i ol3 0.4 ma fr pin. v ol = 0.5 v high level input current1 *2 i ih1 0.4 p af in , xi pin. v ih = v dd1 1.0 v low level input current1 *1 i il1 e 0.4 p af in , xi pin. v il = 0 v, v dd1 1.0 v high level input current2 *2 i ih2 1.0 p a data, clk, le, ps pin. v ih1 = 3.85 v high level input voltage1 v ih1 0.8 u v dd1 4.0 v data, clk, le, ps pin. low level input voltage1 v il1 0 0.2 u v dd1 v data, clk, le, ps pin. high level input voltage2 v ih2 0.8 u v dd1 v dd1 v reset pin. low level input voltage2 v il2 0 0.2 u v dd1 v reset pin. output leak current i l 10 e 4 r 1.0 p a eo, eop, eon pin. v dd1 = 1.0 v to 1.1 v v dd2 = 2.85 v to 3.15 v *1 current from ic *2 current into ic ac performance (unless otherwise specified, v dd1 = 1.00 v to 1.15 v, v dd2 = 2.70 to 3.30 v, t a = e e e e 10 to +50 q q q q c) parameter symbol min. typ. max. unit conditions input frequency 1 f in1 10 70 mhz f in pin, v in = 0.2 v p-p input frequency 2 f in2 10 94 mhz f in pin, v in = 0.2 v p-p , v dd1 = 1.05 v to 1.15 v reference oscillating frequency f xtal 12.8 mhz xi, xo pin
6 p p p p pd2845gr test circuit dc measurement v dd1 f in gnd fr reset eo eop eon pd2845gr xi relay rl1 bs3 gnd c2 c1 x?al d1 xo le clk data ps nc v dd2 bs2 2 gnd 4 5 6 7 8 16 15 14 13 12 11 10 bs1 relay rl1 diode d1 capacitor c1,c2 x?al : srr-204 : 1s945 : 18 pf : 12.8 mhz m ac measurement v dd1 v dd1 f in gnd bnc1 bnc2 sw 1 sw2 sw3 100 pf 1 000 pf 10 pf 10 pf 100 pf 12.8 mhz 1 f fr reset eo eop eon xi xo le clk data ps nc v dd2 v dd2 pd2845gr bnc1 bnc2 sw1 sw2 sw3 : frequency input : frequency output : switch for voltage on/off : desired for ps mode : low : desired for reset mode : high x?al m m 50 w 1 f m
7 p p p p pd2845gr application circuit examples passive filter application example (using internal charge pump) v dd1 f in gnd fr reset eo eop eon xi xo le clk data ps nc v dd2 v dd1 100 pf vco vco out passive filter 100 pf 1 000 pf 10 pf 10 pf 12.8 mhz 1 f v dd2 pd2845gr v dd1 v dd2 xtal : 1.0 to 1.1 v : 2.85 to 3.15 v : 12.8 mhz xtal m 1 f m m controller active filter application example (using external charge pump) vco f in (2 pin) lpf pmos nmos eo eop eon
8 p p p p pd2845gr input timing of serial data latch data clk le read this logic circuit is controlled by a 3-wire serial bus interface with data (12 pin), clk (13 pin) and le (14 pin). on the control setting, binary-coded serial data is input to data pin. this data is read into the shift register at the rising edge of the clk signal input to the clk pin. when the le signal is at the low level, data clk are received into the lsi to be latched at the rising edge of the le signal. while the le signal is at the high level, neither data nor clk signals can be received. caution at the initial v cc supplied time, serial data must be input, because the ic output is unstable on the non-data input stage. [refer to power-save (pin 11) on 12 page]
9 p p p p pd2845gr input signal divider input signal divider obtain the frequency: f p input to phase comparator. this circuit divides input frequency: f in to obtain f p . this block consists of prescaler, 5 bit swallow counter, 13 bit main counter and divide-ratio control circuit. setting numbers ? main counter m = 32 to 8 191 ? swallow counter s = 0 to 31 ? prescaler p = 32, p+1 = 33 total divide ratio nt = s(p+1) + p(m e s) = pm+s = 32 m+s (m t s) ? nt = 1 024 to 262 143 relation between f p and f in f p = f in /(32 m+s) (ex) at f p = 5 khz fin = 70 mhz nt = 70 m/5 k = 14 000 therefore 14 000 32 = 437 ? ? ? 16 nn ms reference counter reference counter obtain the frequency: f r input to phase comparater. this circuit divides the reference oscillating frequency: f xtal of xtal or tcxo to obtain f r . this block consists of 13 bit programmable reference counter and prescaler of divide-by-2. setting number ? 13 bit programmable reference counter r = 2 to 8 191 total reference counter block divide ratio rt = 2 u r ? rt = 4 to 16 382 relation between f r and f xtal f r = (f xtal /2)/r (ex) f r = 5 khz f xtal = 12.8 mhz r = (12.8 mhz/2)/5 khz = 1 280
10 p p p p pd2845gr data format of shift register foundaly constraction of shift register a d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 first bit msb last bit lsb le data clk (1) setting for data selection bit data selection bit: last a bit can govern the latch selection. data selection bits construction and function a function 1 setting for swallow and main counters divide ratio. setting for charge pump output selection. 0 setting for reference counters divide ratio. 0 = low, 1 = high (2) setting for swallow/main counters data and charge pump output selection bit constraction of setting for swallow/main counter and charge pump output selection d22 a d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 a a = 1 charge pump output selection no assigned swallow counter : s (5 bits 0 to 31) main counter : m (13 bits 32 to 8 191) 2 0 2 1 2 2 2 3 2 4 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 caution d19, d20 are not assigned for setting but clk signals must be input because of the bit construction. ? swallow counter data s = (d14 u 2 4 ) + (d15 u 2 3 ) + (d16 u 2 2 ) + (d17 u 2 1 ) + (d18 u 2 0 ) ? main counter data m = (d1 u 2 12 ) + (d2 u 2 11 ) + (d3 u 2 10 ) + (d4 u 2 9 ) + (d5 u 2 8 ) + (d6 u 2 7 ) + (d7 u 2 6 ) + (d8 u 2 5 ) + (d9 u 2 4 ) + (d10 u 2 3 ) + (d11 u 2 2 ) + (d12 u 2 1 ) + (d13 u 2 0 )
11 p p p p pd2845gr nt = 32m + s = 32 u {(d1 u 2 12 ) + (d2 u 2 11 ) + (d3 u 2 10 ) + (d4 u 2 9 ) + (d5 u 2 8 ) + (d6 u 2 7 ) + (d7 u 2 6 ) + (d8 u 2 5 ) + (d9 u 2 4 ) + (d10 u 2 3 ) + (d11 u 2 2 ) + (d12 u 2 1 ) + (d13 u 2 0 )} + {(d14 u 2 4 ) + (d15 u 2 3 ) + (d16 u 2 2 ) + (d17 u 2 1 ) + (d18 u 2 0 )} ? nt = (d1 u 2 17 ) + (d2 u 2 16 ) + (d3 u 2 15 ) + (d4 u 2 14 ) + (d5 u 2 13 ) + (d6 u 2 12 ) + (d7 u 2 11 ) + (d8 u 2 10 ) + (d9 u 2 9 ) + (d10 u 2 8 ) + (d11 u 2 7 ) + (d12 u 2 6 ) + (d13 u 2 5 ) + (d14 u 2 4 ) + (d15 u 2 3 ) + (d16 u 2 2 ) + (d17 u 2 1 ) + (d18 u 2 0 ) thus, total divide ratio of input signal divider nt can be transferred to binary-code in order to setting data d1 to d18 input. (d1 should be top digit and d18 should be bottom digit.) ? charge pump output selection data d22 d21 eo pin (to use internal charge pump) eop, eo pin (to use external charge pump) 0 0 hi- impedance off 0 1 hi-impedance output 1 0 output off 1 1 output output 0 = low, 1 = high (3) setting for reference counter d22 a d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 a a = 0 no assigned reference counter : r (13 bits 2 to 8 191) test bit (fr pin) 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 01 caution d1 to d7 are not assigned for setting but clk signals must be input because of the bit construction. rt = 2 u r ? rt = 2 u {(d10 u 2 12 ) + (d11 u 2 11 ) + (d12 u 2 10 ) + (d13 u 2 9 ) + (d14 u 2 8 ) + (d15 u 2 7 ) + (d16 u 2 6 ) + (d17 u 2 5 ) + (d18 u 2 4 ) + (d19 u 2 3 ) + (d20 u 2 2 ) + (d21 u 2 1 ) + (d22 u 2 0 )} *test bit: for ic tester (fr pin) use or not use (pll operation). for normally pll operation, input d9 = 0, d8 = 1 (fr pin = output l).
12 p p p p pd2845gr power-save and reset power-save (pin 11) power-save-mode can be selected by input data to ps pin. h; operation mode l; power-save-mode on the power-save-mode, reference oscillator and prescaler turn off and error-outs (eo, eop, eon) output hi- impedance but shift register data is remained. serial data can be received in power-save-mode. note: power-save usage for initial v cc supplying to prevent unstable mode at initial v cc supplying, power-save-mode must be selected. after counter data setting, normal operation mode can be selected. reset (pin 5) reset-mode can be selected by input data to reset pin. h; reset-mode l(gnd or open); normal operation. on the reset-mode, reference oscillator/prescalers turn off and error-outs (eo, eop, eon) output hi-impedance. shift-register data is initialized. this reset-mode should be used at lsi testing, normally use as pll, reset pin should be opened or grounded. supplementary explanation: when reset pin bias is switched from h to l, initial divide ratios can be set automatically as follows ? input signal divider: nt = 10372 ? 13 bit programmable reference counter: r = 1 280 (rt = 2 560) these divide ratios make pll loop without controller on condition as follows f in = 51.86 mhz f xtal = 12.8 mhz f p = f r = 5.0 khz
13 p p p p pd2845gr phase comparator phase comparator compares the phase between divided input frequency (f p ) and reference frequency (f r ). this circuit make the change pump output signals according to following detection. *3 to use internal charge pump (passive filter type) *4 to use external charge pump (active filter type) vco should be used as type of higher voltage- higher frequency. eo eop eon eop is pch open drain, eon is nch open drain. eo is output pin of internal charge pump. system application example pager block diagram of direct conversion type lpf 5 p /2 det decoder driver driver bz lcd clock pd2845gr pll lpf m detection eo *3 eop *4 eon *4 f r > f p h h off f r = f p hi-impedance off off f r < f p l off l
14 p p p p pd2845gr package dimensions 16 pin plastic shrink sop (225 mil) item millimeters inches a b c e f g h i j 5.50 max. 0.65 (t.p.) 1.8 max. 1.44 6.2?.3 0.475 max. 0.10 0.9?.2 4.4?.2 m 0.125?.075 n 0.217 max. 0.019 max. 0.005?.003 0.071 max. 0.057 0.244?.012 0.173 0.035 0.004 0.026 (t.p.) p16gm-65-225b-2 p5 ? a g note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. d 0.20?.10 0.008?.004 k 0.15 0.006 +0.10 ?.05 l 0.5?.2 0.020 0.10 0.004 +0.008 ?.009 +0.004 ?.002 +0.009 ?.008 +0.009 ?.008 5 ? p detail of lead end m 16 9 18 e f c n dm b i h k l j
15 p p p p pd2845gr note on correct use (1) observe precautions for handling because of electrostatic sensitive devides. (2) form a ground pattern as wide as possible to minimize ground impedance. (3) connect a bypass capacitor (e. g. 1 000 pf) to the v dd pin. (4) the dc cut capacitor must be each attached to f in , xi and xo pin. (5) external r, c values of loop filter should be determined according to the vco specification. (6) while vco signal is not input to f in pin, power-save-mode must be set. (7) after initially v cc , v dd are supplied, serial data should be input immediately. (before serial data input, lsi operation is unstable or undesired.) recommended soldering conditions this product should be soldered in the following recommended conditions. other soldering method and conditions than the recommended conditions are to be consulted with our sales representatives. p p p p pd2845gr soldering process soldering conditions symbol infrared ray reflow peak packages surface temperature: 235 c or below, reflow time: 30 seconds or below (210 c or higher), number of reflow process: 2, exposure limit*: none ir35-00-2 vps peak packages surface temperature: 215 c or below, reflow time: 40 seconds or below (200 c or higher), number of reflow process: 2, exposure limit*: none vp15-00-2 partial heating method terminal temperature: 300 c or below, flow time: 3 seconds or below, exposure limit*: none *: exposure limit before soldering after dry-package is opened. storage conditions: 25 c and relative humidity at 65 % or less. note apply only a single process at once, except for partial heating method. for details of recommended soldering conditions for surface mounting, refer to information document semiconductor device mounting technology manual (c10535e).
p p p p pd2845gr no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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